Sunday, November 9, 2014

Memahami macam-macam tegangan dan signal driver panel LCD


Panel kaca LCD agar dapat menyala mendapat macam-macam tegangan dan di-drive oleh macam-macam bentuk pulsa. Setiap model mungkin cara kerjanya sedikit berbeda. Sedikit coretan dibawah ini mungkin dapat membantu untuk memamahaminya.
image
image
VDD VDD is the logic supply input for the scan driver.
VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP high-voltage driver outputs.
VOFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP high-voltage driver outputs.
STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to generate the high-voltage STVP output.
CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing of the CKV1 and CKVB1 outputs, which change state (by first sharing charge) on its falling edge.
CPV2 Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2 outputs, which change state (by first sharing charge) on its falling edge.
EN Enables the MAX17121. Drive EN high to start up the MAX17121 after a delay time, which is set by a capacitor at DLY.
CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high impedance whenever CKV1 is high impedance.
CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high impedance whenever CKV2 is high impedance.
CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2 and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2, sharing charge between the capacitive loads on these two outputs.
CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing charge between the capacitive loads on these two outputs.
STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high impedance.
DLY Startup Delay Setting. Connect a capacitor to adjust the delay
DISH VOFF Discharge Connection. Pulling DISH below ground activates an internal connection between VOFF and GND, rapidly discharging the VOFF supply. Typically, DISH is capacitively connected to VDD, so that when VDD falls, VOFF is discharged.
VCOM Operational Amplifier Output
image

image
CKV High-Voltage, Gate-Pulse Output. When enabled, CKV toggles between its high state (connected to GON) and its low state (connected to GOFF) on each falling edge of the CPV input. Further, CKV is high impedance whenever CPV and OE are both low or whenever CPV is low and OECON is high.
CKVCS CKV Charge-Sharing Connection. CKVCS connects to CKV whenever CKV is high impedance to allow connection to CKVB, sharing charge between the capacitive loads on these two outputs.
CKVBCS CKVB Charge-Sharing Connection. CKVBCS connects to CKVB whenever CKVB is high impedance to allow connection to CKV, sharing charge between the capacitive loads on these two outputs.
CKVB High-Voltage, Gate-Pulse Output. CKVB is the inverse of CKV during active states and is high impedance whenever CKV is high impedance.
STVP High-Voltage, Start-Pulse Output. STVP is low (connected to GOFF) whenever STV is low and is high (connected to GON) only when STV is high and CPV and OE are both low. When STV is high and either CPV or OE is high, STVP is high impedance.
STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to generate the high-voltage STVP output.
OECON Active-Low, Output-Enable Timing Input. OECON is driven by an RC-filtered version of the OE input signal. If OE remains high long enough for the resistor to charge the capacitor up to the OECON threshold, the OE signal is masked until OE goes low and the capacitor is discharged below the threshold through the resistor.
OE Active-High, Gate-Pulse Output Enable. CKV and CKVB leave the high-impedance charge-sharing state on the rising edge of OE.
CPV Vertical Clock-Pulse Input. CPV controls the timing of the CKV and CKVB outputs that change state (by first sharing charge) on its falling edge.
GND Logic Ground
DISH GOFF Discharge Input. Pulling DISH below ground activates an internal connection between GOFF and GND, rapidly discharging the GOFF supply. Typically, DISH is capacitively connected to IN, so that when VIN falls GOFF is discharged.
VDD Supply Input. Logic supply input for the VCOM calibrator. Bypass to GND through a minimum 0.1μF capacitor.
WPN Active-Low, Write-Protect Input. When WPN is low, I2C commands are ignored and the VCOM calibrator settings cannot be modified.
SCLS Alternate I2C-Compatible Clock Input. When WPN is high, SCLS connects to SCL to drive SCL from an alternate clock source.
SCL I2C-Compatible Clock Input and Output
SDA I2C-Compatible Serial Bidirectional Data Line
WPP Write-Protect Output. WPP is the inverse of WPN. It can be used to control active-high, write-protect inputs on other devices.
SET Full-Scale, Sink-Current Adjustment Input. Connect a resistor, RSET, from SET to GND to set the full-scale adjustable sink current that is VBOOST / (20 x RSET). IOUT is equal to the current through RSET.
VL 3.3V On-Chip Regulator Output. This regulator powers internal analog circuitry for the step-up regulator, op amp, and VCOM calibrator. External loads up to 10mA can be powered. Bypass VL to GND with a 0.22μF or greater ceramic capacitor.
BGND Amplifier Ground
BOOST Operational Amplifier Supply Input. Connect to VMAIN (Figure 2) and bypass to BGND with a 1μF or greater ceramic capacitor.
OUT Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp input POS (between BOOST and GND) that determines the VCOM output voltage. IOUT lowers the divider voltage by a programmable amount.
POS Operational Amplifier Noninverting Input
NEG Operational Amplifier Inverting Input
VCOM Operational Amplifier Output
SHDN Shutdown Control Input. Pull SHDN low to disable the step-up regulator. The VCOM calibrator, op amp, and scan driver functions remain enabled.
IN Step-Up Regulator Supply Input. Bypass IN to AGND (pin 34) with a 1μF or greater ceramic capacitor.
LX Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.
PGND Power Ground. Source connection of the internal step-up regulator power switch.
FB Feedback Input. Reference voltage is 1.24V nominal. Connect external resistor-divider midpoint here and minimize trace area. Set VOUT according to: VOUT = 1.24V (1 + R1/R2).
COMP Compensation Input for Error Amplifier. Connect a series RC from COMP to AGND. Typical values are 180k and 470pF.
AGND Ground
GOFF Gate-Off Supply. GOFF is the negative supply voltage for the CKV, CKVB, and STVP high-voltage driver outputs. Bypass to PGND with a minimum of 0.1μF ceramic capacitor.
GON Gate-On Supply. GON is the positive supply voltage for the CKV, CKVB, and STVP high-voltage driver outputs. Bypass to VMAIN or PGND with a minimum of 0.1μF ceramic capacitor.
EP Exposed Backside Pad. Connect to the analog ground plane through multiple vias to enhance thermal performance.

image
CKVB1 High-Voltage Scan-Drive Output. CKVB1 is the inverse of CKV1 during active states and is high impedance whenever CKV1 is high impedance.
STVP High-Voltage Scan-Drive Output. STVP is connected to VOFF when STV is low and is connected to VON when STV is high and CPV1 is low. When both STV and CPV1 are high, STVP is high impedance.
CKVB2 High-Voltage Scan-Drive Output. CKVB2 is the inverse of CKV2 during active states and is high impedance whenever CKV2 is high impedance.
CKVBCS2 CKVB2 Charge-Sharing Connection. CKVBCS2 connects to CKVCS2 whenever CPV2 and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKV2 to connect to CKVB2, sharing charge between the capacitive loads on these two outputs.
CKVCS2 CKV2 Charge-Sharing Connection. CKVCS2 connects to CKVBCS2 whenever CPV2 and STV are both low (to make CKV2 and CKVB2 high impedance) to allow CKVB2 to connect to CKV2, sharing charge between the capacitive loads on these two outputs.
CKV2 High-Voltage Scan-Drive Output. When enabled, CKV2 toggles between its high state (connected to VON) and its low state (connected to VOFF) on each falling edge of the CPV2 input. Further, CKV2 is high impedance whenever CPV2 and STV are both low.
STV Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to generatethe high-voltage STVP output.
CPV1 Vertical Clock-Pulse Input. CPV1 controls the timing of the CKV1 and CKVB1 outputs, which change state (by first sharing charge) on its falling edge.
CPV2 Vertical Clock-Pulse Input. CPV2 controls the timing of the CKV2 and CKVB2 outputs, which change state (by first sharing charge) on its falling edge.
N.C. Not Connected
EN Enables the MAX17121. Drive EN high to start up the MAX17121 after a delay time, which is set by a capacitor at DLY.
DLY Startup Delay Setting. Connect a capacitor to adjust the delay based on tDELAY= CDLYx 410kI.
GND Ground
DISH VOFF Discharge Connection. Pulling DISH below ground activates an internal connection between VOFF and GND, rapidly discharging the VOFF supply. Typically, DISH is capacitively connected to VDD, so that when VDD falls, VOFF is discharged.
VDD Supply Input. VDD is the logic supply input for the scan driver. Bypass to GND through a minimum 0.1FF capacitor.
VOFF Gate-Off Supply. VOFF is the negative supply voltage for the CKV_, CKVB_, and STVP high-voltage driver outputs. Bypass to GND with a minimum of 1FF ceramic capacitor.
VON Gate-On Supply. VON is the positive supply voltage for the CKV_, CKVB_, and STVP high-voltage driver outputs. Bypass to GND with a minimum of 1FF ceramic capacitor.
CKV1 High-Voltage Scan-Drive Output. When enabled, CKV1 toggles between its high state (connected to VON) and its low state (connected to VOFF) on each falling edge of the CPV1 input. Further, CKV1 is high impedance whenever CPV1 and STV are both low.
CKVCS1 CKV1 Charge-Sharing Connection. CKVCS1 connects to CKVBCS1 whenever CPV1 and STV are both low (to make CKV1 and CKVB1 high impedance) to allow CKVB1 to connect to CKV1, sharing charge between the capacitive loads on these two outputs.
CKVBCS1 CKVB1 Charge-Sharing Connection. CKVBCS1 connects to CKVCS1 whenever CPV1 and STV are both low (to make CKV1 and CKVB1 high impedance) to allow CKV1 to connect to CKVB1, sharing charge between the capacitive loads on these two outputs.
EP Exposed Pad. EP is not connected in the IC. The EP should be connected to the ground plane on the PCB to improve thermal performance.




**********************************************

No comments: